z z z z z z z z z z z z z z z z z z z z M13S2561616A 4M x 16 Bit x 4 Banks Double Data Rate SDRAM JEDEC Standard Internal pipelined double-data-rate architecture, two d.

Pin Name Function Address inputs - Row address A0~A12 - Column address A0~A8 A10/AP : AUTO Precharge BA0, BA1 : Bank selects (4 Banks) Data-in/Data-out Row address strobe Column address strobe Write enable Ground Power Bi-directional Data Strobe. LDQ.

M13S256328A

M13S128168A

M13S128324A

M13S32321A

M13S5121632A

M13S64164A-4BG2Y

M13S64164A-4TG2Y

M13S64164A-5BG

M13S64164A-5BG2Y

M13S64164A-5TG

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